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Securities Times reporter Wang Yiming
Advanced packaging has become the focus of the semiconductor industry.
In the past month, traditional OSATs (outsourced semiconductor assembly and testing factories) such as Tongfu Microelectronics, TSMC, Amkor, ASE (Advanced Semiconductor Engineering), and Huatian Technology, as well as leading wafer fabs, have successively announced plans to invest resources in the layout of advanced packaging-related technologies and production capacities. These projects are all targeted at applications in high-performance computing, AI, and other fields.
Talking about this phenomenon, Wang Peng, a researcher at the Beijing Academy of Social Sciences, recently told the Securities Times reporter that various applications such as AI, the Internet of Things, and communications have increasingly high requirements for computing power. In the "post-Moore era", the upgrading speed of advanced processes has gradually slowed down, and at the same time, the marginal cost of moving forward has become increasingly high. Against this background, using advanced packaging technology to improve the overall performance of chips has become an important trend in the technological development of the integrated circuit industry. The recent increase in investment in advanced packaging by the above-mentioned manufacturers is a reflection of this trend.
"Currently, international leading wafer fabs and OSATs are relatively ahead in advanced packaging technology, and these enterprises are mainly targeting fields such as high-performance computing and HBM (High Bandwidth Memory). The capacity layout of domestic OSATs also covers areas such as AI chips and storage, but their technology is still weak compared with international leading enterprises. However, as domestic enterprises continue to strengthen technological research and development and talent training, and with the continuous growth of domestic chip demand and policy support, the domestic advanced packaging industry is entering a stage of rapid development, and is expected to narrow the gap with international enterprises in the long term." Yuan Shuai, deputy secretary-general of the Zhongguancun Internet of Things Industry Alliance, analyzed.
Major manufacturers successively step up efforts in advanced packaging
Traditional packaging is mainly lead frame-based packaging, including DIP, SOP, QFP, QFN and other packaging forms, whose functions are mainly chip protection, scale enlargement, and electrical connection.
Advanced packaging uses advanced designs and processes to perform package-level reconstruction of chips; in comparison, advanced packaging also has the characteristics of significantly reducing the area of the packaged chip, accommodating more I/O ports of the chip, reducing the comprehensive manufacturing cost of the chip, and improving the interconnection capability between chips, thereby enhancing system performance. Generally speaking, any of the four basic elements of Bump, RDL, Wafer, and TSV can be called advanced packaging.
"Similar to the continuous iteration of front-end advanced processes, advanced packaging is also a concept that changes over the long term. Currently, in terms of technical types, advanced packaging technologies such as flip-chip, wafer-level, system-level, fan-out, and 2.5D/3D have become one of the best choices to continue Moore's Law." A person from the semiconductor packaging industry explained to the Securities Times reporter.
Against this background, major manufacturers have continued to layout related technologies and production capacities in recent years. Especially in the past month, related projects are accelerating. On October 10, the Tongfu Microelectronics advanced packaging and testing project with a total investment of 3.52 billion yuan officially started, and the future products of this project will be widely used in high-performance computing, artificial intelligence, network communication and other fields. On October 9, ASE's new K28 factory was groundbreaking, which will increase investment in advanced packaging terminal testing and AI chip high-performance computing. On October 4, TSMC and Amkor, a major U.S. packaging and testing company, signed a memorandum of understanding, and the two will cooperate in integrated fan-out (InFO) and CoWoS advanced packaging to meet the capacity needs of common customers such as AI. On September 22, the second phase of the Huatian Nanjing Integrated Circuit Advanced Packaging and Testing Industry Base project with an investment of 10 billion yuan was groundbreaking, and future products will target storage, radio frequency, computing power, AI and other fields.
In Wang Peng's view, leading wafer fabs and OSATs are expressing their optimism about the industry through practical actions. From the dynamics in recent years, domestic leading packaging and testing manufacturers such as Tongfu Microelectronics, JCET, and Huatian Technology have continuously improved their competitiveness in the field of advanced packaging through independent research and development and cooperation with internationally leading enterprises; at the same time, leading wafer fabs such as TSMC, Intel, and Samsung are also actively deploying advanced packaging. Among them, TSMC established an integrated interconnection and packaging technology integration department as early as 2008. These enterprises have consolidated their leading position in the field of advanced packaging through technological innovation and capacity expansion.
Advanced packaging
Market share is rising rapidly
What is the future scale of the industry? According to Yole Group's prediction, the global advanced packaging market size will grow from $37.8 billion in 2023 to $69.5 billion in 2029, with a compound annual growth rate of 10.7% during this period. The proportion of advanced packaging in the overall packaging market will reach 51.03% in 2025. The institution predicts that in 2024, major manufacturers such as TSMC, Intel, Samsung, ASE, Amkor, and JCET will invest a total of about $11.5 billion in the field of advanced packaging.
According to the observation of the Securities Times reporter, although all are deploying advanced packaging, there are differences in technology choices among major manufacturers. Zhang Xiaorong, dean of the Deep Technology Research Institute, believes that there is no absolute advantage or disadvantage in the technical types of advanced packaging, because different technologies are suitable for different application scenarios. The choice of flip-chip, wafer-level, system-level, fan-out, 2.5D/3D and other technologies depends on specific application requirements and technical maturity.
However, with the rapid development of the technology and market demand for high-computing-power chips, the corresponding 2.5D and 3D packaging technologies are becoming increasingly popular. IDC predicts that from 2023 to 2028, the 2.5D/3D packaging market is expected to grow at a compound annual growth rate of 22%, making it a highly concerned field in the semiconductor packaging and testing market.
Among 2.5D/3D packaging technologies, TSMC's CoWoS is the most well-known to the outside world, which was developed by TSMC in 2012. After technical upgrades such as cost reduction, TSMC defeated its competitor Samsung with this technology in 2016 and won all foundry orders for Apple's A-series processors. From 2016 to now, while the process technology has been continuously improved, TSMC's advanced packaging technology has also been upgraded. Today's CoWoS can not only save space and achieve the high interconnection density and short-distance connection required by HBM, but also package chips with different processes together, meeting the accelerated computing needs of AI, GPU, etc. while controlling costs. The complementarity of advanced process technology and advanced packaging technology has allowed international giants such as NVIDIA and Apple to form long-term in-depth cooperation with TSMC. Among them, NVIDIA's B-series products (including the latest GB200, etc.) extensively use CoWoS technology.
How popular is CoWoS? On October 17, TSMC Chairman Wei Zhejia said at the performance briefing that customer demand for CoWoS advanced packaging far exceeds supply. Despite increasing CoWoS capacity by more than 2 times this year, it is still in short supply, and TSMC will still fully respond to customers' demand for CoWoS capacity.
DIGITIMES pointed out in its August report that AI chips are highly dependent on TSMC's CoWoS packaging technology. Therefore, the compound annual growth rate of TSMC's CoWoS capacity expansion from 2023 to 2028 will exceed 50%, while the compound annual growth rate of advanced process expansion below 5nm in the wafer foundry industry from 2023 to 2028 will reach 23%.
Multiple technologies are blooming
"Some key processes of certain technologies in advanced packaging need to be completed on the front-end chip manufacturing platform. For example, the CoW part of CoWoS is too precise and can only be manufactured by TSMC, so the capacity will be in short supply, which is also the inherent advantage of wafer fabs compared with OSATs. The subsequent planning of TSMC's 3D platform SoIC has also been put on the agenda. In addition to TSMC, Intel and Samsung are also developing and promoting their own 2.5D/3D packaging technologies." The above-mentioned person from the semiconductor packaging industry told the Securities Times reporter.
Overall, traditional OSATs still occupy most of the market share. According to the 2023 global outsourced packaging and testing market share list released by Core Thoughts Research Institute, among the top ten outsourced packaging and testing companies, there are 5 from Taiwan, China (among which ASE ranks first), with a market share of 37.73%; 4 from Chinese mainland are on the list, with a market share of 25.83%, among which JCET, Tongfu Microelectronics, and Huatian Technology rank third, fourth, and sixth respectively. TSMC's advanced packaging revenue in 2023 exceeded $6 billion, and if it participates in the outsourced packaging ranking, it will rank second in the world.
Facing the entry of wafer fabs, traditional OSATs have also made efforts. For example, ASE, Powertech Technology, Siliconware Precision Industries, etc. are actively deploying fan-out panel-level packaging (FOPLP). FOPLP is regarded as a rising star in advanced packaging technology due to its unique advantages such as lower cost and greater flexibility.
At the same time, first-tier packaging factories in Chinese mainland have also developed new processes with certain characteristics. According to JCET's 2024 semi-annual report, in the field of high-performance advanced packaging, the company's XDFOI Chiplet high-density multi-dimensional heterogeneous integration series processes have entered the stable mass production stage as planned. This technology is a high-density heterogeneous integration solution for Chiplet with extremely high density and multi-fan-out packaging, covering 2D, 2.5D, and 3D integration technologies. After continuous research and development and customer product verification, XDFOI has been applied in high-performance computing, artificial intelligence, 5G, automotive electronics and other fields.
"Whether it is 2.5D or 3D, it is now in a state of full bloom. Everyone has researched from last year to the start of production this year, the trend has been formed, and the income is still in the initial stage, but the accumulation of customer projects and the number of mass production imports are increasing. The main application is data centers. The demand is not only AI itself, but also with the increase in data volume, the requirements for advanced packaging of computing and storage are getting higher and higher." A relevant person in charge of JCET pointed out at the performance briefing.
Tongfu Microelectronics is AMD's largest packaging and testing supplier, accounting for more than 80% of its total orders. According to disclosures, the company's high-performance packaging business maintained steady growth in the first half of the year. At the technical level, the company has vigorously developed fan-out, wafer-level, flip-chip and other packaging technologies and expanded their production capacities. In addition, it has actively deployed top packaging technologies such as Chiplet and 2D+. Previously, the company's ultra-large-size 2D+ packaging technology and 3D stacking packaging technology have passed verification.
Domestic advanced packaging capacity is scarce
Institutional data shows that from the perspective of the structure of the packaging market, advanced packaging accounted for 49% of the global packaging market in 2023, and about 39% in China, which is still lower than the global level. Compared with international giants, what are the advantages and disadvantages of China's packaging industry currently?
"The advantages of domestic manufacturers in the field of advanced packaging compared with international manufacturers lie in their understanding of the local market, policy support, and cost advantages, but they are relatively weak in technological research and development and talent reserves." Yuan Shuai believes.
In Zhang Xiaorong's view, packaging technology was once one of the links in China's semiconductor industry with the smallest gap from the world's top technologies. In recent years, with the entry of international mainstream wafer fabs into advanced packaging, the technical gap has a tendency to be further widened. To make up for technical shortcomings, it is necessary to increase R&D investment, strengthen cooperation and exchanges with internationally advanced enterprises, introduce and cultivate high-end talents, and promote in-depth integration of industry, education, and research. From the perspective of the industrial chain, domestic independent research and development capabilities in high-end equipment and materials need to be improved, and some key core technologies and equipment still rely on imports.
Regarding the future industry trend, AI is still an unavoidable variable. Currently, the revenue source of generative AI technology is not yet stable. Will the advanced packaging capacity that is being rushed to be put into production face overcapacity due to the risk of declining AI demand in the future?
The first question to answer is: when will the demand for AI chips decline? So far, the industry is optimistic. Gartner predicts that the global AI chip market size will increase by 33% in 2024 to $71.3 billion, and is expected to further grow by 29% in 2025 to $92 billion; the server AI chip market size will reach $21 billion in 2024 and is expected to reach $33 billion in 2028.
"In the past, the growth momentum of the global semiconductor industry mostly came from To C products. This year, in addition to the recovery of consumer electronics, part of the growth is driven by To B, that is, the huge demand for high-end computing power chips brought by computing power infrastructure, which are mainly purchased by enterprises. To analyze the sustainability of AI chip growth, we need to pay attention to these procurement demands. At present, enterprises' demand for training their own AI models is still strong. If future performance declines and cash is tight, procurement will inevitably be affected." Wang Xiaolong, director of the Enterprise Department of Xinmou Research, previously told reporters.
Wang Peng pointed out that on the one hand, deploying advanced packaging requires a lot of talent and investment costs, and the number of enterprises capable of deployment is very limited, which to a certain extent limits excessive capacity expansion; on the other hand, enterprises can timely adjust their capacity layout and product lines according to changes in demand. If the AI chip-related market lacks sufficient carrying capacity, advanced packaging capacity can also be transferred to other application markets.
"It should also be pointed out that for the domestic market, with the continuous development of the semiconductor industry, advanced packaging capacity is more scarce. Therefore, I believe that there is no need to consider the problem of overcapacity in the short and medium term." Wang Peng said.
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